The present invention relates generally to non-volatile memories and in particular the present invention relates to trimming non-volatile reference memory cells.
Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. Computers often contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in a row and column fashion. Each memory cell includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into erasable blocks. Each of the memory cells can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by an erase operation. Thus, the data in a cell is determined by the presence or absence of the charge in the floating gate.
To program a memory cell, a high positive voltage Vg is applied to the control gate of the cell. In addition, a moderate positive voltage is applied to the drain (Vd) and the source voltage (Vs) and the substrate voltage (Vsub) are at ground level. These conditions result in the inducement of hot electron injection in the channel region near the drain region of the memory cell. These high-energy electrons travel through the thin gate oxide towards the positive voltage present on the control gate and collect on the floating gate. The electrons remain on the floating gate and function to reduce the effective threshold voltage of the cell as compared to a cell that has not been programmed. A programmed non-volatile memory cell is said to be at a logic level of xe2x80x9c0xe2x80x9d.
In flash memories, blocks of memory cells are erased in groups. This is achieved by putting a negative voltage on the word lines of an entire block and coupling the source connection of the entire block to Vcc (power supply), or higher. This creates a field that removes electrons from the floating gates of the memory elements. In an erased state, the memory cells can be activated using a lower control gate voltage. An erased non-volatile memory cell is said to be at a logic level of xe2x80x9c1xe2x80x9d.
Non-volatile memory systems, including flash memory systems, use a variety of sense amplifiers to verify the state of memory cells in a memory array. Verification of a non-volatile memory cell is accomplished by applying a potential to the control gate of the cell to be verified and then using a sense amplifier to compare a current generated by the cell with a known current from a reference cell. The reference cell is a non-volatile memory cell or bit that has a predefined charge that is set or trimmed by the manufacture of the memory to produce a specific reference current in response to a known gate voltage. The sense amplifier determines whether the memory cell to be verified draws more or less current than the reference current. By doing this, the sense amplifier determines if the memory cell is in a programmed state or an erased state.
The reference cell or cells are pre-programmed by the memory manufactures. The time needed to program these cells to a desired voltage threshold (Vt) can be significant. Moreover, the longer it takes to program the cells the less memory devices can be produced for sale. Therefore, the longer the period of time needed to program reference cells, the more the memory device costs to make.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved method of pre-programming reference cells.
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
A method of trimming a non-volatile memory cell is disclosed comprising erasing the memory cell below a desired voltage threshold (Vt) level, applying a program pulse to the memory cell, reading the memory cell, comparing a current conducted by the memory cell with an externally provided reference current, using a sense amplifier that is internal to a memory device that contains the memory cell, producing a digital output based on the comparison of the currents and applying successive program pulses until the digital output changes from one logic state to another.
A method of trimming a flash reference cell comprising erasing the reference cell below a desired Vt level, applying a program pulse to the reference cell to increase a floating gate charge of the reference cell, accessing the reference cell to create a cell current in a bitline coupled to a drain of the reference cell, comparing the cell current with an externally provided reference current, wherein the reference current is indicative of a desired memory cell current and applying further program pulses to the reference cell when the cell current is less than the reference current.
A method of trimming a flash floating gate memory cell comprising erasing the floating gate of the memory cell such that the memory cell remains turned off when a predetermined voltage is applied to a control gate of the memory cell, applying an external reference current to a sense amplifier, wherein the sense amplifier is internal to a memory device that contains the memory cell, providing a program pulse to the memory cell to increase a charge on the floating gate of the memory cell, coupling the predetermined voltage to the control gate, comparing a digitline current provided by the memory cell with the reference current using the sense amplifier and providing additional program pulses to the memory cell while the digitline current is less than the reference current.
A method of trimming non-volatile reference bits of a memory device comprising erasing each reference bit below a desired voltage threshold, applying a low level program pulse to each reference bit, coupling a predetermined access voltage to control gates of each reference bit to create a bit current in associated bitlines coupled to each reference bit, applying an external provided reference current to the memory device, comparing the external reference current to the bit currents in each of the bitlines with sense amplifiers of the memory device and applying additional program pulses to reference bits coupled to bitlines having bit current levels less than the reference current.
In one embodiment, a reference cell programming system comprises a memory device and a tester. The memory device includes a memory array having at least one non-volatile reference cell and a sense amplifier coupled to sense a cell current conducted by the reference cell. The tester is coupled to the memory to program the reference cells to a designated charge level. Moreover, the tester provides a reference current that is coupled to the sense amplifier and monitors an output of the sense amplifier.
In another embodiment, a non-volatile memory device comprises a primary memory array, at least one non-volatile reference memory cell and sense circuitry. The primary memory array has a plurality of memory cell. The sense circuitry is used to monitor the logic state of the memory cells. In addition, the memory device has an input connection to couple an external reference current to the sense circuitry to be used during the programming of the reference memory cell.
In another embodiment, a reference program tester to pre-program a reference memory cell in a memory device comprises a reference current output, a command output and an input. The reference current output is used to supply a reference current to a sense amplifier of the memory device during pre-programming of the reference memory cell. The command output is used to provide control commands to control circuitry of the memory device and the input is used to receive a logic signal from the memory device. Moreover, the control commands are based on the logic signals received by the input.